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1/29 april 2004 m48t37y m48t37v 5.0 or 3.3v, 256 kbit (32 kbit x8) timekeeper ? sram features summary integrated ultra-low power sram, real time clock, power-fail control circuit, and battery frequency test output for real time clock software calibration year 2 000 compliant automatic power-fail chip deselect and write protection watchdog timer write protect voltage (v pfd = power-fail deselect voltage): ? m48t37y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v ? m48t37v: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v packaging includes a 44-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery and crystal microprocessor power-on reset (valid even during battery back-up mode) programmable alarm output active in the battery back-up mode battery low flag figure 1. package 44 1 snaphat (sh) battery/crystal soh44 (mh) 44-pin soic
m48t37y, m48t37v 2/29 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. write enable controlled, write ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9. back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 programmable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 v cc noise and negative going transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10.supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12.clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/29 m48t37y, m48t37v dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13.ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15.soh44 ? 44-lead plastic small outline, 4-socket snaphat, package outline. . . . . . . 24 table 14. soh44 ? 44-lead plastic small outline, 4-socket snaphat, package mech. data . . . 24 figure 16.sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline . . . . . . . 25 table 15. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data. . . . 25 figure 17.sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline . . . . . . 26 table 16. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data. . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 18. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m48t37y, m48t37v 4/29 summary description the m48t37y/v timekeeper ? ram is a 32 kb x8 non-volatile static ram and real time clock. the monolithic chip is available in a special package which provides a highly integrated battery backed- up memory and real time clock solution. the 44-lead, 330mil soic package provides sock- ets with gold-plated contacts at both ends for di- rect connection to a separate snaphat housing containing the battery and crystal. the unique de- sign allows the snaphat ? battery/crystal pack- age to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sep- arately in plastic anti-static tubes or in tape &reel form. for the 44-lead soic, the battery/crystal package (e.g., snaphat) part number is ?m4t28- br12sh? or ?m4t32-br12sh? (see table 18., page 27 ). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. figure 2. logic diagram table 1. signal names ai02172 8 dq0-dq7 w v cc m48t37y m48t37v v ss g e wdi rst irq/ft 15 a0-a14 a0-a14 address inputs dq0-dq7 data inputs / outputs rst reset output (open drain) irq /ft interrupt / frequency test output (open drain) wdi watchdog input e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally
5/29 m48t37y, m48t37v figure 3. soic connections ai02174 22 44 43 v ss 1 a1 a7 a4 a3 a2 a6 a5 a13 nc a8 a9 nc a11 g e v cc m48t37y m48t37v 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 a12 a14 irq/ft nc 3 4 38 37 42 41 a0 dq0 dq7 dq5 dq1 dq2 dq3 dq4 dq6 16 17 18 19 20 27 26 25 24 23 wdi nc nc rst nc nc nc a10 nc nc w nc nc nc
m48t37y, m48t37v 6/29 figure 4. block diagram ai03253 lithium cell oscillator and clock chain v pfd rst v cc v ss 32,768 hz crystal voltage sense and switching circuitry 16 x 8 biport sram array 32,752 x 8 sram array a0-a14 dq0-dq7 e w g power irq/ft wdi
7/29 m48t37y, m48t37v operation modes as figure 4., page 6 shows, the static memory ar- ray and the quartz controlled clock oscillator of the m48t37y/v are integrated on one silicon chip. the memory locations that provide user accessi- ble bytewide? clock information are in the bytes with addresses 7ff1 and 7ff9h-7fffh (lo- cated in table 5., page 13 ). the clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour bcd format. cor- rections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are made automat- ically. byte 7ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. byte 7ff7h contains the watchdog timer setting. the watchdog timer redirects an out-of-control mi- croprocessor and provides a reset or interrupt to it. bytes 7ff2h-7ff5h are reserved for clock alarm programming. these bytes can be used to set the alarm. this will generate an active low signal on the irq /ft pin when the alarm bytes match the date, hours, minutes, and seconds of the clock. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the m48t37y/v includes a clock control cir- cuit which updates the clock bytes with current in- formation once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t37y/v also has its own power-fail de- tect circuit. the control circuitry constantly moni- tors the single v cc supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc . as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operation until val- id power returns. table 2. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 13., page 23 for details. mode v cc e g w dq0-dq7 power deselect 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
m48t37y, m48t37v 8/29 read mode the m48t37y/v is in the read mode whenever write enable (w ) is high and chip enable (e ) is low. the unique address specified by the 15 ad- dress inputs defines which one of the 32,752 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and output enable (g ) access times are also satisfied. if the e and g ac- cess times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e and g remain active, output data will remain valid for out- put data hold time (t axqx ) but will be indetermi- nate until the next address access. figure 5. read mode ac waveforms note: write enable (w ) = high. table 3. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) m48t37y m48t37v unit ?70 ?100 min max min max t avav read cycle time 70 100 ns t av qv address valid to output valid 70 100 ns t elqv chip enable low to output valid 70 100 ns t glqv output enable low to output valid 35 50 ns t elqx (2) chip enable low to output transition 5 10 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 25 50 ns t ghqz (2) output enable high to output hi-z 25 40 ns t axqx address transition to output transition 10 10 ns ai00925 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a14 e g dq0-dq7 valid
9/29 m48t37y, m48t37v write mode the m48t37y/v is in the write mode whenever w and e are low. the start of a write is refer- enced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of anoth- er read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; however, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 6. write enable controlled, write ac waveform figure 7. chip enable controlled, write ac waveforms ai00926 tavav twhax tdvwh data input a0-a14 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai00927 tavav tehax tdveh a0-a14 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48t37y, m48t37v 10/29 table 4. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48t37y m48t37v unit ?70 ?100 min max min max t avav write cycle time 70 100 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 50 80 ns t eleh chip enable low to chip enable high 55 80 ns t whax write enable high to address transition 0 10 ns t ehax chip enable high to address transition 0 10 ns t dvwh input valid to write enable high 30 50 ns t dveh input valid to chip enable high 30 50 ns t whdx write enable high to input transition 5 5 ns t ehdx chip enable high to input transition 5 5 ns t wlqz (2,3) write enable low to output hi-z 25 50 ns t av wh address valid to write enable high 60 80 ns t av eh address valid to chip enable high 60 80 ns t whqx (2,3) write enable high to output transition 5 10 ns
11/29 m48t37y, m48t37v data retention mode with valid v cc applied, the m48t37y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as ?don't care.? note : a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t37y/v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48t37y/v for an accumulated period of at least 7 years at room temperature when v cc is less than v so . as sys- tem power returns and v cc rises above v so , the battery is disconnected and the power supply is switched to external v cc . normal ram operation can resume t rec after v cc reaches v pfd (max). for more information on battery storage life refer to the application note an1012.
m48t37y, m48t37v 12/29 clock operations reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register 7ff8h. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating will resume within a second af- ter the bit is reset to a '0.' setting the clock bit d7 of the control register (7ff8h) is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the time keeper reg- isters. the user can then load them with the cor- rect day, date, and time data in 24 hour bcd format (see table 5., page 13 ). resetting the write bit to a '0' then transfers the values of all time registers (7ff1h, 7ff9h-7fffh) to the actual timekeeper c ounters and allows normal opera- tion to resume. after the write bit is reset, the next clock update will occur in approximately one second. note : upon power-up following a power failure, both the write bit and the read bit will be reset to '0.' stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. when reset to a '0,' the m48t37y/v oscillator starts within one second. note : it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st).
13/29 m48t37y, m48t37v table 5. register map keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to '0' bl = battery low flag (read only) bmb0-bmb4 = watchdog multiplier bits afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits wds = watchdog steering bit abe = alarm in battery back-up mode enable bit rpt1-rpt4 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) z = '0' and are read only address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7fffh 10 years year year 00-99 7ffeh 0 0 0 10 m month month 01-12 7ffdh 0 0 10 date date: day of month date 01-31 7ffch 0 ft 0 0 0 day of week day 01-7 7ffbh 0 0 10 hours hours hours 00-23 7ffah 0 10 minutes minutes min 00-59 7ff9h st 10 seconds seconds sec 00-59 7ff8h w r s calibration control 7ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7ff6hafe0abe00000interrupts 7ff5h rpt4 0 aiarm 10 date alarm date alarm date 01-31 7ff4h rpt3 0 aiarm 10 hours alarm hours alarm hour 00-23 7ff3h rpt2 alarm 10 minutes alarm minutes alarm min 00-59 7ff2h rpt1 alarm 10 seconds alarm seconds alarm sec 00-59 7ff1h 1000 year 100 year century 00-99 7ff0h wdf af z bl z z z z flags
m48t37y, m48t37v 14/29 setting the alarm clock registers 7ff5h-7ff2h contain the alarm set- tings. the alarm can be configured to go off at a predetermined time on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the m48t37y/v is in the battery back-up mode of op- eration to serve as a system wake-up call. rpt1-rpt4 put the alarm in the repeat mode of operation. table 6 shows the possible configura- tions. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. note: user must transition address (or toggle chip enable) to see flag bit change. when the clock information matches the alarm clock settings based on the match criteria defined by rpt1-rpt4, af is set. if afe is also set, the alarm condition activates the irq /ft pin. to dis- able alarm, write '0' to the alarm date registers and rpt1-4. the alarm flag and the irq /ft out- put are cleared by a read to the flags register as shown in figure 8 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft pin can also be activated in the bat- tery back-up mode. the irq /ft will go low if an alarm occurs and both the alarm in battery back- up mode enable (abe) and the afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot -up to determine if an alarm was generated while the m48t37y/v was in the dese- lect mode during power-up. figure 9., page 15 il- lustrates the back-up mode alarm timing. figure 8. alarm interrupt reset waveform table 6. alarm repeat modes rpt4 rpt3 rpt2 rpt1 alarm activated 1 1 1 1 once per second 1 1 1 0 once per minute 1 1 0 0 once per hour 1 0 0 0 once per day 0 0 0 0 once per month ai01677b a0-a14 active flag bit address 7ff0h irq/ft 15ns min
15/29 m48t37y, m48t37v figure 9. back-up mode alarm waveforms calibrating the clock the m48t37y/v is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t37y/v improves to better than +1/?2 ppm at 25 c. the oscillation rate of any crystal changes with temperature (see figure 11., page 19 ). most clock chips compensate for crystal frequency and tem- perature shift error with cumbersome trim capaci- tors. the m48t37y/v design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 12., page 19 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register 7ff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is the sign bit; '1' in- dicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 osc illator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 (64 minutes x 60 seconds/ minute x 32,768 cycles/sec ond) actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjust- ment per calibration step in the calibration register. assuming that the oscillator is in fact running at ex- actly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t37y/v may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like www broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his en- vironment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accesses the calibration byte. ai03254b v cc irq/ft trec v pfd (max) v pfd (min) abe, afe bit in interrupt register af bit in flags register high-z v so high-z
m48t37y, m48t37v 16/29 the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft pin. the pin will toggle at 512 hz when the stop bit (st, d7 of 7ff9h) is '0' the frequency test bit (ft, d6 of 7ffch) is '1,' the alarm flag enable bit (afe, d7 of 7ff6h) is '0,' and the watchdog steering bit (wds, d7 of 7ff7h) is '1' or the watchdog register is reset (7ff7h=0). any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a ?10(wr001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output fre- quency. the irq /ft pin is an open drain output which re- quires a pull-up resistor for proper operation. a 500-10k ? resistor is recommended in order to control the rise time. the ft bit is cleared on pow- er-down. for more information on calibration, see the appli- cation note an934, ?timek eeper calibration.? watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the eight-bit watchdog register, ad- dress 7ff7h. the five bits (bmb4-bmb0) that store a binary multiplier and the two lower order bits (rb1-rb0) select the resolution, where 00 = 1 / 16 second, 01 = 1 / 4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five- bit multiplier value with the resolution. (for exam- ple: writing 00001110 in the watchdog register = 3x1, or 3 seconds). note : accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m48t37y/v sets the watch- dog flag (wdf) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flags register (address 7ff0h). note: user must transition address (or toggle chip enable) to see flag bit change. reset will not occur unless the addresses are sta- ble at the flag location for at least 15ns while the device is in the read mode as shown in figure 10., page 18 . the most significant bit of the watchdog register is the watchdog steering bit. when set to a '0,' the watchdog will activate the irq /ft pin when timed- out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for a dura- tion of t rec . the watchdog register, the ft bit, afe bit, and abe bit will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer resets when the microproces- sor performs a re-write of the watchdog register or an edge transition (low to high / high to low) on the wdi pin occurs. the time-out period then starts over. the watchdog timer is disabled by writing a value of 00000000 to the eight bits in the watchdog reg- ister. should the watchdog timer time-out, a value of 00h needs to be written to the watchdog regis- ter in order to clear the irq/ft pin. the watchdog function is automatically disabled upon power-down and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. the wdi pin should be connected to v ss if not used. power-on reset the m48t37y/v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd . rst is valid for all v cc conditions. the rst pin is an open drain output and an appropriate resistor to v cc should be chosen to control rise time (see figure 14., page 23 ).
17/29 m48t37y, m48t37v programmable interrupts the m48t37y/v provides two programmable in- terrupts: an alarm and a watchdog. when an inter- rupt condition occurs, the m48t37y/v sets the appropriate flag bit in the flag register 7ff0h. the interrupt enable bits (afe and abe) in 7ff6h and the watchdog steering (wds) bit in 7ff7h al- low the interrupt to activate the irq /ft pin. the alarm flag and the irq /ft output are cleared by a read to the flags register. an interrupt con- dition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the read mode as shown in fig- ure 8., page 14 . the irq /ft pin is an open drain output and re- quires a pull-up resistor (10k ? recommended) to v cc . the pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled. battery low flag the m48t37y/v automatically performs periodic battery voltage monitoring upon power-up. the battery low flag (bl), bit d4 of the flags register 7ff0h, will be asserted high if the snaphat ? battery is found to be less than approximately 2.5v. the bl flag will remain active until comple- tion of battery replacement and subsequent bat- tery low monitoring tests during the next power-up sequence. if a battery low is generated during a power-up se- quence, this indicates the battery voltage is below 2.5v (approximately), which may be insufficient to maintain data integrity. data should be considered suspect and verified as correct. a fresh battery should be installed. the snaphat top may be re- placed while vcc is applied to the device. note: this will cause the clock to lose time during the interval the battery/crystal is removed. note: battery monitoring is a useful technique only when performed periodically. the m48t37y/v only monitors the battery when a nominal v cc is applied to the device. thus applications which re- quire extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is in- dicated, data integrity should be verified upon power-up via a checksu m or other technique. initial power-on defaults upon application of power to the device, the fol- lowing register bits are set to a '0' state: wds; bmb0-bmb4; rb0-rb1; afe; abe; w; r; and ft (see table 7 ). table 7. default values note: 1. wds, bmb0-bmb4, rbo, rb1. 2. state of other control bits undefined. 3. state of other control bits remains unchanged. 4. assuming these bits set to '1' prior to power-down. condition w r ft afe abe watchdog register (1) initial power-up (battery attach for snaphat) (2) 00000 0 subsequent power-up / reset (3) 00000 0 power-down (4) 00011 0
m48t37y, m48t37v 18/29 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 10 ) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 10. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
19/29 m48t37y, m48t37v figure 11. crystal accuracy across temperature figure 12. clock calibration ai00999 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 ? f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ai00594b normal positive calibration negative calibration
m48t37y, m48t37v 20/29 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 8. absolute maximum ratings note: 1. for so package, standard (snpb) lead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180 c for between 90 to 150 seconds). 2. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exceed 245 c for greater than 30 seconds). caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 ?40 to 85 c t stg storage temperature (v cc off, oscillator off) snaphat ? ?40 to 85 c soic ?55 to 125 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages m48t37y ?0.3 to 7 v m48t37v ?0.3 to 4.6 v v cc supply voltage m48t37y ?0.3 to 7 v m48t37v ?0.3 to 4.6 v i o output current 10 ma p d power dissipation 1 w
21/29 m48t37y, m48t37v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 9. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 13. ac testing load circuit note: excluding open-drain output pins 1. ; 50pf for m48t37v. table 10. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48t37y m48t37v unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) grade 1 0 to 70 0 to 70 c grade 6 ?40 to 85 ?40 to 85 c load capacitance (c l ) 100 50 pf input rise and fall times 10 10 ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai02325 c l = 100pf (1) c l includes jig capacitance 645 ? device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
m48t37y, m48t37v 22/29 table 11. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. 3. negative spikes of ?1v allowed for up to 10ns once per cycle. symbol parameter test condition (1) m48t37y m48t37v unit ?70 ?100 minmaxminmax i li (2) input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current outputs open 50 33 ma i cc1 supply current (standby) ttl e = v ih 32ma i cc2 supply current (standby) cmos e = v cc ? 0.2v 32ma v il (3) input low voltage ?0.3 0.8 ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage (standard) i ol = 2.1ma 0.4 0.4 v output low voltage (open drain) i ol = 10ma 0.4 0.4 v v oh (3) output high voltage i oh = ?1ma 2.4 2.4 v
23/29 m48t37y, m48t37v figure 14. power down/up mode ac waveforms table 12. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. t rec (min) = 20ms for industrial temperature range - grade 6 device. table 13. power down/up trip points dc characteristics note: all voltages referenced to v ss . 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. using larger m4t32-br12sh6 snaphat top (recommended for industrial temperature range - grade 6 device). 3. at 25c, v cc = 0v. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec (4) v pfd (max) to rst high 40 200 ms symbol parameter (1) min typ max unit v pfd power-fail deselect voltage m48t37y 4.2 4.4 4.5 v m48t37v 2.7 2.9 3.0 v v so battery back-up switchover voltage m48t37y v bat v m48t37v v pfd ?100mv v t dr (3) expected data retention time grade 1 5 7 years grade 6 10 (2) years ai03078 v cc inputs rst outputs don't care high-z tf tfb tr trec trb tdr valid valid v pfd (max) v pfd (min) v so valid valid
m48t37y, m48t37v 24/29 package mechanical information figure 15. soh44 ? 44-lead plastic small outline, 4-socket snaphat, package outline note: drawing is not to scale. table 14. soh44 ? 44-lead plastic small outline, 4-socket snaphat, package mech. data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e0.81? ?0.032? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n44 44 cp 0.10 0.004 soh-a e n d c l a1 1 h a cp be a2 eb
25/29 m48t37y, m48t37v figure 16. sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 15. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
m48t37y, m48t37v 26/29 figure 17. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 16. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
27/29 m48t37y, m48t37v part numbering table 17. ordering information scheme note: 1. the soic package (soh44) requires the snaphat ? battery package which is ordered separately under the part number ?m4txx- br12sh? in plastic tube or ?m4txx-br12shtr? in tape & reel form (see table 18 ). caution : do not place the snaphat battery package ?m4txx-br12sh? in conductive foam as it will drain the lithium button-cell bat- tery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 18. snaphat battery table example: m48t 37y ?70 mh 1 e device type m48t supply voltage and write protect voltage 37y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 37v = v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed ?70 = 70ns (37y) ?10 = 100ns (37v) package mh (1) = soh44 temperature range 1 = 0 to 70c 6 = ?40 to 85c shipping method blank = tubes (not for new design - use e) e = lead-free package (eco pack ? ), tubes f = lead-free package (eco pack ? ), tape & reel tr = tape & reel (not for new design - use f) part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
m48t37y, m48t37v 28/29 revision history table 19. document revision history date rev. # revision details december 1999 1.0 first issue 07-feb-00 2.0 from preliminary data to data sheet; battery low flag paragraph changed; 100ns speed class identifier changed (tables 3 , 4 ) 11-jul-00 2.1 t fb changed (table 12 ); watchdog timer paragraph changed 19-jun-01 3.0 reformatted; added temp./voltage info. to tables (table 10 , 11 , 3 , 4 , 12 , 13 ) 06-aug-01 3.1 fix text for setting the alarm clock (figure 8 ) 15-jan-02 3.2 fix footnote numbering (table 17 ) 20-may-02 3.3 modify reflow time and temperature footnote (table 8 ) 31-mar-03 4.0 v2.2 template applied; data retention condition updated (table 13 ) 01-apr-04 5.0 reformatted; updated with lead-free package information (table 8 , 17 )
29/29 m48t37y, m48t37v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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